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GSM Power Management System ADP3522
FEATURES Handles all GSM Baseband Power Management 6 LDOs Optimized for Specific GSM Subsystems Li-Ion Battery Charge Function Optimized for the AD20msp430 Baseband Chipset Reduced Package Size: 5 mm 5 mm LFCSP-32 APPLICATIONS GSM/GPRS Handsets
PWRONKEY ROWX
FUNCTIONAL BLOCK DIAGRAM
VBAT VBAT2 VRTCIN
POWER-UP SEQUENCING AND PROTECTION LOGIC
SIM LDO
VSIM SIMVSEL
DIGITAL CORE LDO
VCORE
GENERAL DESCRIPTION
PWRONIN ANALOG LDO TCXOEN SIMEN RESCAP MEMORY LDO RTC LDO REF BUFFER VMEM TCXO LDO VAN
The ADP3522 is a multifunction power system chip optimized for GSM/GPRS handsets, especially those based on the Analog Devices AD20msp430 system solution with 1.8 V digital baseband processors, such as the AD6525, AD6526, and AD6528. It contains six LDOs, one to power each of the critical GSM subblocks. Sophisticated controls are available for powerup during battery charging, keypad interface, and RTC alarm. The charge circuit maintains low current charging during the initial charge phase and provides an end of charge (EOC) signal when a Li-Ion battery is being charged. This product also meets the market trend of reduced size with a new LFCSP package. Its footprint is only 5 mm 5 mm and yet offers excellent thermal performance due to the exposed die attached paddle. The ADP3522 is specified over the temperature range of -20C to +85C.
VTCXO
VRTC
REFOUT RESET
CHRDET EOC CHGEN BATSNS ISENSE GATEIN CHRIN GATEDR AGND BATTERY CHARGE CONTROLLER BATTERY VOLTAGE DIVIDER
MVBAT
DGND
ADP3522
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADP3522-SPECIFICATIONS (-20 C < T < +85 C, VBAT = VBAT2 = 3 V-5.5 V, CVSIM = CVCORE = CVAN =
A
ELECTRICAL CHARACTERISTICS
Parameter
1
CVMEM = 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum loads applied on all outputs, unless otherwise noted.)
Conditions Min Typ Max Unit
Symbol
SHUTDOWN SUPPLY CURRENT VBAT 2.5 V (Deep Discharged Lockout Active) 2.5 V < VBAT 3.2 V (UVLO Active) VBAT > 3.2 V OPERATING GROUND CURRENT VSIM, VCORE, VMEM, VRTC On All LDOs On All LDOs On UVLO ON THRESHOLD UVLO HYSTERESIS DEEP DISCHARGED LOCKOUT ON THRESHOLD DEEP DISCHARGED LOCKOUT HYSTERESIS INPUT HIGH VOLTAGE PWRONIN TCXOEN, SIMEN, CHGEN, GATEIN, SIMVSEL INPUT LOW VOLTAGE (PWRONIN, TCXOEN, SIMEN, CHGEN, SIMVSEL) PWRONIN Pin Pull-Down Resistor INPUT HIGH BIAS CURRENT (TCXOEN, SIMEN, CHGEN, SIMVSEL ) INPUT LOW BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, SIMVSEL) PWRONKEY INPUT HIGH VOLTAGE PWRONKEY INPUT LOW VOLTAGE PWRONKEY INPUT PULL-UP RESISTANCE TO VBAT THERMAL SHUTDOWN THRESHOLD2 THERMAL SHUTDOWN HYSTERESIS
ICC VBAT = VBAT2 = 2.3 V VBAT = VBAT2 = 3.0 V VBAT = VBAT2 = 4.0 V IGND VBAT = 3.6 V Minimum Loads Minimum Loads Maximum Loads Rising Edge 15 30 45 225 345 1.0 3.2 200 VDDLO Falling Edge 2.4 100 VIH 1.0 1.5 VIL 0.3 V V V 2.75 40 55 80 300 450 3.0 3.3 A A A A A % of Max Load V mV V mV
VUVLO
RPD IIH
200
1000
5000 1.0
k A
IIL
-1.0
A
VIH VIL
0.7
VBAT 0.3 VBAT 130
V V k C C
70
100 160 45
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ADP3522
Parameter Symbol Conditions Min Typ Max Unit
ROWX CHARACTERISTICS ROWX Output Low Voltage ROWX Output High Leakage Current
VOL IIH
PWRONKEY = Low IOL = 200 A PWRONKEY = High V(ROWX) = 5 V
0.4 1
V A
SIM CARD LDO (VSIM) Output Voltage Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage
VSIM VSIM VSIM VSIM CO VDO
Line, Load, Temperature SIMVSEL = Low Line, Load, Temperature SIMVSEL = High 50 A ILOAD 20 mA VBAT = 3.6 V
1.70 2.80
1.80 2.85 2 2
1.90 2.92
V V mV mV F
2.2 VO = VINITIAL - 100 mV, ILOAD = 20 mA, VSIM = 2.85 V 1.75
35
100
mV
DIGITAL CORE LDO (VCORE) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability RTC LDO REAL-TIME CLOCK LDO/ COIN CELL CHARGER (VRTC) Maximum Output Voltage Maximum Output Current Off Reverse Input Current Output Capacitor Required for Stability ANALOG LDO (VAN) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Ripple Rejection Output Noise Voltage
VCORE Line, Load, Temperature VCORE VCORE 50 A ILOAD 100 mA VBAT = 3.6 V CO
1.80 2 8
1.85
V mV mV F
2.2
VRTC IL CO
1 A ILOAD 10 A VRTC = 0.5 V VRTC = 1.90 V, VBAT = 1.70 V, TA = 25C
1.86
1.95 4.0
2.0
V mA A F
0.5 0.1
VAN VAN VAN CO VBAT/ VAN3 VNOISE
Line, Load, Temperature 50 A ILOAD 180 mA, VBAT = 3.6 V
2.50
2.55 2 11
2.60
V mV mV F dB
2.2 f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 180 mA VBAT = 3.6 V VO = VINITIAL - 100 mV, ILOAD = 180 mA 65 80
V rms 400 mV
Dropout Voltage
160
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ADP3522 ELECTRICAL CHARACTERISTICS
Parameter Symbol
(-20 C < TA < +85 C, VBAT = VBAT2 = 3 V-5.5 V, CVSIM = CVCORE = CVAN = CVMEM =
1 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum loads applied on
all outputs, unless otherwise noted.)
Conditions Min Typ Max Unit
TCXO LDO (VTCXO) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage MEMORY LDO (VMEM) Output Voltage-3 Output Voltage-1.8 Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage-3 REFOUT Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Output Current Delay Time per Unit Capacitance Applied to RESCAP Pin BATTERY VOLTAGE DIVIDER Divider Ratio Divider Impedance at MVBAT Divider Leakage Current Divider Resistance
VTCXO VTCXO VTCXO CO VDO VBAT/ VTCXO VNOISE
Line, Load, Temperature 50 A ILOAD 20 mA, VBAT = 3.6 V
2.711
2.75 2 2
2.789
V mV mV F
0.22 VO = VINITIAL - 100 mV ILOAD = 20 mA f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 20 mA, VBAT = 3.6 V Line, Load, Temperature Line, Load, Temperature 50 A < ILOAD < 150 mA VBAT = 3.6 V 2.2 VO = VINITIAL - 100 mV ILOAD = 150 mA 160 360 160 65 80 300
mV dB V rms
VMEM VMEM VMEM VMEM CO
2.740 1.80
2.80 1.85 2 12
2.850 1.90
V V mV mV F mV
VREFOUT VREFOUT VREFOUT VBAT/ VREFOUT CO VNOISE VOH VOL IOL/IOH tD
Line, Load, Temperature Min Load 0 A < ILOAD < 50 A VBAT = 3.6 V f = 217 Hz (t = 4.6 ms)
1.19
1.21 0.2 0.5 75
1.23
V mV mV dB pF V rms V V mA ms/nF
65 100
f = 10 Hz to 100 kHz IOH = +500 A IOL = -500 A VOL= 0.25 V, VOH = VMEM - 0.25 V
40 VMEM - 0.25 0.25 1 0.6 1.2 2.4
BATSNS/
TCXOEN = High
2.32 59.5
2.35 85 300
2.37 110 1 385 k A k
MVBAT ZO TCXOEN = Low TCXOEN = High
215
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ADP3522
Parameter Symbol Conditions 4.35 V CHRIN 10 V3 Min Typ Max Unit
BATTERY CHARGER Charger Output Voltage
BATSNS
4.150 4.155
4.200
4.250 4.250
V V
Load Regulation
BATSNS
CHGEN = Low, No Load CHRIN = 10 V CHGEN = Low, No Load 0C < TA < 50C CHRIN = 5 V
0 CHRIN - ISENSE < Current Limit Threshold
15
mV
CHGEN = Low CHRDET On Threshold CHRDET Hysteresis CHRDET Off Delay4 CHRIN Supply Current Current Limit Threshold High Current Limit (UVLO Not Active) CHRIN - VBAT CHRIN < VBAT CHRIN = 5 V CHRIN - ISENSE CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low 0C < TA < 50C VBAT = 2 V CHGEN = Low CHRIN = 5 V - 10 V CHRIN - ISENSE 142 160 190 mV 30 90 40 6 0.6 150 mV mV ms/nF mA
149
160
180
mV
Low Current Limit (UVLO Active) ISENSE Bias Current EOC Signal Threshold
20
35
mV A
200 CHRIN = 5 V DC VBAT > 4.0 V CHGEN = Low CHGEN = Low CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = High IOH = -1 mA CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = 1 mA IOH = -250 A IOL = 250 A 14 35
mV
EOC Reset Threshold GATEDR Transition Time
VBAT t R , tF VOH
3.82 0.1
3.96
4.10 1
V s V
GATEDR High Voltage
4.5
GATEDR Low Voltage
VOL
0.5
V
Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET)
VOH VOL
VMEM - 0.25 0.25
V V
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125C. Operation beyond 125C could cause permanent damage to the device. 3 No isolation diode is present between the charger input and the battery. 4 Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice.
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-5-
ADP3522
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description
Voltage on Any Pin with Respect to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +10 V Voltage on Any Pin May Not Exceed VBAT, with the Following Exceptions: CHRIN, BASE, ISENSE Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Operating Ambient Temperature Range . . . . . -20C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C 5 mm) JA, Thermal Impedance (LFCSP 5 mm 4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 32C/W 2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Lead Temperature Range (Soldering, 60 sec.) . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17, 24, 32 18 19 20
SIMEN VRTCIN VRTC BATSNS MVBAT CHRDET CHRIN SIMVSEL GATEDR GATEIN DGND ISENSE EOC CHGEN RESCAP RESET NC VSIM VBAT2 VMEM VCORE VBAT VAN VTCXO REFOUT AGND TCXOEN PWRONIN PWRONKEY ROWX
SIM LDO Enable RTC LDO Input Voltage Real-Time Clock Supply/ Coin Cell Battery Charger Battery Voltage Sense Input Divided Battery Voltage Output Charge Detect Output Charger Input Voltage Programs VSIM Output; Low: 1.8 V Charger Drive Output Microprocessor Charger Gate Control Input Digital Ground Charge Current Sense Input End of Charge Output Charge Enable Control Input Reset Delay Time Main Reset, Open Drain No Connection SIM LDO Output Battery Input Voltage 2 Memory LDO Output Digital Core LDO Output Battery Input Voltage Analog LDO Output TCXO LDO Output Output Reference Analog Ground TCXO LDO Enable and MVBAT Enable Power On/Off Signal from Microprocessor Power On/Off Key Power Key Interface Output
ORDERING GUIDE
Model ADP3522ACP-3 ADP3522ACP-1.8
Memory LDO Output 2.80 V 1.80 V
Temperature Range -20C to +85C -20C to +85C
Package Option CP-32 CP-32
PIN CONFIGURATION
32 NC 31 ROWX 30 PWRONKEY 29 PWRONIN
28 TCXOEN 27 AGND
26 REFOUT
25 VTCXO
21 22
24 NC 23 VAN 22 VBAT 21 VCORE 20 VMEM 19 VBAT2 18 VSIM 17 NC
SIMEN 1 VRTCIN 2 VRTC 3 BATSNS 4 MVBAT 5 CHRDET 6 CHRIN 7 SIMVSEL 8
GATEDR 9
23 25 26 27 28 29 30 31
PIN 1 INDICATOR
ADP3522
TOP VIEW
(Not to Scale) TOP VIEW
GATEIN 10 DGND 11 ISENSE 12
EOC 13 CHGEN 14
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3522 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
RESCAP 15
RESET 16
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Typical Performance Characteristics-ADP3522
450 400 350 300 A 250 IGND - 200 150 100 50 0 3.0 10 3.5 4.0 4.5 VBAT - V 5.0 5.5 0 0.5 1.0 VRTC - V 1.5 2.0 VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = L, TCXOEN = L) VSIM, VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = H, TCXOEN = L) 1000
A IRTC -
10000 ALL LDO, MVBAT, REFOUT, ON_MIN_LOAD (SIMEN = H, TCXOEN = H) +85 C -20 C
A REVERSE LEAKAGE CURRENT -
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE - C RTC REVERSE LEAKAGE (VBAT = 2.3V) RTC REVERSE LEAKAGE (VBAT = FLOAT)
+25 C 100
TPC 1. Ground Current vs. Battery Voltage
TPC 2. RTC I/V Characteristic
TPC 3. VRTC Reverse Leakage Current vs. Temperature
180 160 VTCXO
3.2
VMEM VAN
3.2
DROPOUT VOLTAGE - mV
140 120 100 80 60 40 20 0 0 VSIM
VBAT 3.0 3.0
VBAT
VTCXO VMEM
10mV/DIV 10mV/DIV
VTCXO VMEM
10mV/DIV 10mV/DIV
50 100 150 LOAD CURRENT - mA
200
TIME - 100 s/DIV
TIME - 100 s/DIV
TPC 4. Dropout Voltage vs. Load Current
TPC 5. Line Transient Response, Minimum Loads
TPC 6. Line Transient Response, Maximum Loads
3.2
3.2 20mA VBAT VBAT 3.0 VAN VCORE VSIM 10mV/DIV 10mV/DIV 10mV/DIV VAN VCORE VSIM 10mV/DIV 10mV/DIV 10mV/DIV VTCXO 10mV/DIV LOAD 2mA
3.0
TIME - 100 s/DIV
TIME - 100 s/DIV
TIME - 200 s/DIV
TPC 7. Line Transient Response, Minimum Loads
TPC 8. Line Transient Response, Maximum Loads
TPC 9. VTCXO Load Step
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ADP3522
100mA 150mA
20mA LOAD 2mA
LOAD 15mA
LOAD 10mA
VSIM
10mV/DIV
VMEM 20mV/DIV
VCORE 10mV/DIV
TIME - 200 s/DIV
TIME - 200 s/DIV
TIME - 200 s/DIV
TPC 10. VSIM Load Step
TPC 11. VMEM Load Step
TPC 12. VCORE Load Setup
180mA LOAD 18mA
PWRONIN (2V/DIV)
PWRONIN (2V/DIV)
VAN (100mV/DIV)
VSIM = 2.8 (100mV/DIV)
20mV/DIV
VMEM = 1.8 (100mV/DIV)
VCORE (100mV/DIV)
TIME - 200 s/DIV
TIME - 400 s/DIV
TIME - 200 s/DIV
TPC 13. VAN Load Step
TPC 14. Turn On Transient by PWRONIN, Minimum Load (Part 1)
TPC 15. Turn On Transient by PWRONIN, Minimum Load (Part 2)
PWRONIN (2V/DIV)
PWRONIN (2V/DIV)
PWRONIN (2V/DIV)
REFOUT (100mV/DIV)
VAN (100mV/DIV) VSIM = 1.8 (100V/DIV)
VMEM = 2.8 (100mV/DIV)
VSIM = 2.8 (100mV/DIV)
VTCXO (100mV/DIV)
VCORE (100mV/DIV)
TIME - 100 s/DIV
TIME - 1ms/DIV
TIME - 20 s/DIV
TPC 16. Turn On Transient by PWRONIN, Minimum Load (Part 3)
TPC 17. Turn On Transient by PWRONIN, Minimum Load (Part 4)
TPC 18. Turn On Transient by PWRONIN, Maximum Load (Part 1)
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ADP3522
PWRONIN (2V/DIV)
PWRONIN (2V/DIV) PWRONIN (2V/DIV)
REFOUT (100mV/DIV)
VSIM = 1.8 (100mV/DIV)
VMEM = 2.8(100mV/DIV)
VMEM = 1.8 (100mV/DIV)
VTCXO (100mV/DIV)
TIME - 20 s/DIV
TIME - 100 s/DIV
TIME - 20 s/DIV
TPC 19. Turn On Transient by PWRONIN, Maximum Load (Part 2)
TPC 20. Turn On Transient by PWRONIN, Maximum Load (Part 3)
TPC 21. Turn On Transient by PWRONIN, Maximum Load (Part 4)
80 70 VAN VTCXO
80 REFOUT 70
RIPPLE REJECTION - dB
VOLTAGE SPECTRAL NOISE DENSITY - nV/ Hz
600 FULL LOAD MLCC CAPS VAN TCXO
500
RIPPLE REJECTION - dB
60 VCORE 50 40 30 20 10 0 4 10 100 1k 10k FREQUENCY - Hz 100k MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS REFOUT
60 50 VSIM 40 30 20 VTCXO 10 VMEM 0 2.5 2.6 2.7 VSIM = 2.8V FREQ = 217Hz, MAX LOADS 3.1 3.2 3.3 VAN
400
300
200 REF 100
2.8 2.9 3.0 VBAT - V
0 10
100
1k 10k FREQUENCY - Hz
100k
TPC 22. Ripple Rejection vs. Frequency
TPC 23. Ripple Rejection vs. Battery Voltage
TPC 24. Output Noise Density
4.25 4.24 4.23
4.24 VIN = 5.0V RSENSE = 250m
4.24 RSENSE = 250m
OUTPUT VOLTAGE - V
4.22 4.21 4.20 4.19 4.18 4.17 4.16 4.15 -40
OUTPUT VOLTAGE - V
CHARGER VOUT - V
4.23
4.23
4.22
4.22
ILOAD = 500mA
4.21
ILOAD = 10mA 4.21
4.20 -20 0 20 40 60 80 100 120 0 200 TEMPERATURE - C 400 ILOAD - mA 600 800
4.20 5 6 7 8 INPUT VOLTAGE - V 9 10
TPC 25. Charger VOUT vs. Temperature, VIN = 5.0 V, ILOAD = 10 mA
TPC 26. Charger VOUT vs. ILOAD (VIN = 5.0 V)
TPC 27. Charger VOUT vs. VIN
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ADP3522
Table I. LDO Control Logic
PWRONKEY
PWRONIN
CHRDET
TCXOEN
REFOUT
STATE NO. PHONE STATUS
State No. 1 Battery Deep Discharged State No. 2 Phone Off State No. 3 Phone Off, Turn-On Allowed State No. 4 Charger Applied State No. 5 Phone Turned On by User Key State No. 6 Deep Sleep State No. 7 Active State No. 8 Reset SIM Card
L H
X L
X X
X X
X X
X X
X X
OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF
H H
H H
L H
H X
L X
X X
X L
OFF OFF OFF OFF ON ON
ON ON
OFF OFF OFF OFF ON ON ON ON*
H H H H
H H H H
X L L L
L H H H
X H H H
X L H H
L H H L
OFF ON ON OFF
ON ON ON ON
ON ON ON ON
ON ON ON ON
ON
ON
ON
ON*
OFF OFF OFF OFF ON ON ON ON ON ON ON ON
*The state of MVBAT is determined by TCXOEN. When TCXOEN is high, MVBAT is ON.
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MVBAT
VTCXO
VCORE
SIMEN
VMEM
DDLO
UVLO
VRTC
VSIM
VAN
ADP3522
VBAT
VRTCIN
VBAT2
SIMVSEL
SIM LDO VBAT DEEP DISCHARGED UVLO QS PWRONKEY ROWX R DIGITAL CORE LDO OVERTEMP SHUTDOWN VBAT VREF EN 1M ANALOG LDO SIMEN CHARGER DETECT VBAT VREF EN AGND OUT VAN DGND OUT PG VCORE UVLO VREF EN VSEL OUT
VSIM
110k
DGND
PWRONIN
TCXOEN RESCAP CHRDET EOC CHGEN GATEIN BATSNS ISENSE GATEDR CHRIN Li-ION BATTERY CHARGE CONTROLLER AND PROCESSOR CHARGE INTERFACE TCXO LDO RESET GENERATOR VBAT VREF EN AGND MEMORY LDO VBAT VREF EN DGND RTC LDO VBAT VREF EN DGND OUT VRTC OUT VMEM OUT VTCXO RESET
EN REF BUFFER 1.21V
REFOUT
MVBAT
AGND DGND
AGND
Figure 1. Functional Block Diagram
REV. 0
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ADP3522
PWRON POWERKEY ROWX R8 10 C8 0.1 F
PWRONIN AGND NC PWRONKEY REFOUT TCXOEN VTCXO ROWX
CLKON REFOUT VTCXO C9 0.22 F
SIMEN
SIMEN VRTCIN
NC VAN VBAT C10 2.2 F VAN
VRTC COIN CELL MVBAT CHRDET CHRIN SIMSEL R1 0.25
C1 0.1 F
VRTC BATSNS MVBAT CHRDET CHRIN
GATEIN ISENSE CHGEN
ADP3522
VCORE VMEM VBAT2 VSIM
RESCAP
VCORE VMEM
VSIM
GATEDR
Q1 SI3441 D1 BAT1000 Li OR NiMH BATTERY C3 10 F C4 0.1 F C5 2.2 F C6 2.2 F
EOC
C2 1nF
DGND
RESET
SIMVSEL
NC
RESET CHGEN EOC C7 2.2 F
GATEIN
Figure 2. Typical Application Circuit
THEORY OF OPERATION
The ADP3522 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows a block diagram of the ADP3522. The ADP3522 contains several blocks, such as: * Six low dropout regulators (SIM, core, analog, crystal oscillator, memory, real-time clock) * Reset generator * Buffered precision reference * Lithium ion charge controller and processor interface * Power on/off logic * Undervoltage lockout * Deep discharge lockout These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3522 combines the benefits of both worlds by providing an integrated standard product where every block is optimized to operate in a GSM environment while maintaining a cost competitive solution. Figure 2 shows the external circuitry associated with the ADP3522. Only a minimal number of support components are required.
Input Voltage
ADP3522 needs to dissipate. The thermal impedance of the CSP package is 32C/W for a JEDEC standard 4-layer board. The end of charge voltage for high capacity NiMH cells can be as high as 5.5 V. This results in a worst-case power dissipation for the ADP3522-1.8 to be as high as 1.6 W for NiMH cells. The power dissipation for the ADP3522-3 is slightly lower at 1.45 W. A fully charged Li-Ion battery is 4.25 V, where the ADP3522-3 can dissipate a maximum power of 0.85 W. However, the ADP3522-1.8 can have a maximum dissipation of 1.0 W. High battery voltages normally occur when the battery is being charged and the handset is not in conversation mode. In this mode, there is a relatively light load on the LDOs. The worstcase power dissipation should be calculated based on the actual load currents and voltages used. Figure 3 shows the maximum power dissipation as a function of the input voltage. Figure 4 shows the maximum allowable power dissipation as a function of the ambient temperature.
Low Dropout Regulators (LDOs)
The ADP3522 high performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 F tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, SIM, and analog LDOs. A 0.22 F capacitor is recommended for the TCXO LDO.
The input voltage range of the ADP3522 is 3 V to 5.5 V and is optimized for a single Li-Ion cell or three NiMH cells. The type of battery, the SIM LDO output voltage, and the memory LDO output voltage will all affect the amount of power that the -12- REV. 0
ADP3522
Digital Core LDO (VCORE)
The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads as this LDO is on whenever the handset is switched on.
Memory LDO (VMEM)
Applying a low to SIMEN shuts down the SIM LDO. A discharge circuit is active when SIMEN is low. This pulls the SIM LDO's output down when the LDO is disabled. SIMVSEL allows the SIM LDO to be programmed for either 1.8 V or 2.8 V. Asserting a high on SIMVSEL sets the output for 2.8 V. SIMEN and SIMVSEL allow the baseband processor to properly sequence the SIM supply when determining which type of SIM module is present.
Reference Output (REFOUT)
The memory LDO supplies the system memory as well as the subsystems of the baseband processor including memory IO, display, and melody interfaces. It is capable of delivering up to 150 mA of current and is available for either 1.8 V or 3 V based systems. The LDO has also been optimized for low quiescent current and will power up at the same time as the core LDO.
Analog LDO (VAN)
This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the ripple coming from the RF power amplifier. VAN is rated to 180 mA, which is sufficient to supply the analog section of the baseband converter, such as the AD6521, as well as the microphone and speaker.
TCXO LDO (VTCXO)
The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% overtemperature. The maximum output current of the REFOUT supply is limited to 50 A.
Power ON/OFF
The ADP3522 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3522 in three different ways: * Pulling the PWRONKEY low * Pulling the PWRONIN high * CHRIN exceeds CHRDET threshold Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn on all the LDOs, except the SIM LDO, as long as the PWRONKEY is held low. When the VCORE LDO comes into regulation, the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3522 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY and press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/OFF control. Pulling the PWRONIN pin high is how the alarm in the realtime clock module will turn the handset on. Asserting PWRONIN will turn the core and memory LDOs on, starting up the baseband processor.
The TCXO LDO is intended as a supply for a temperature compensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 20 mA of output current and is turned on along with the analog LDO when TCXOEN is asserted. Note that the ADP3522 has been optimized for use with the AD6534 (Othello OneTM).
RTC LDO (VRTC)
The RTC LDO is capable of charging rechargeable Lithium or capacitor-type backup coin cells to run the real-time clock module. The RTC LDO supplies current both for charging the coin cell and for the RTC module. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module.
SIM LDO (VSIM)
The SIM LDO generates the voltage needed for 1.8 V or 3 V SIMs. It is rated for 20 mA of supply current and can be controlled completely independently of the other LDOs.
1.8 1.6
POWER DISSIPATION - W
1.8 1.6
POWER DISSIPATION - W
1.4 1.2
ADP3522-1.8
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -20
LFCSP 32 C/W
ADP3522-2.8 1.0 0.8 0.6 0.4 0.2 0 3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
20
40
60
80
INPUT VOLTAGE - V
AMBIENT TEMPERATURE - C
Figure 3. Power Dissipation vs. Input Voltage
Figure 4. Allowable Package Power Dissipation vs. Temperature
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ADP3522
NONCHARGING MODE
CHARGER DETECTED CHRIN > BATSNS YES
NO
VBAT > UVLO
YES
NO BATTERY TYPE LOW CURRENT CHARGE MODE Li+ VSENSE = 20mV CHGEN = LOW CHGEN = HIGH NiMH
HIGH CURRENT CHARGE MODE VSENSE = 160mV
NiMH CHARGING MODE GATEIN = PULSED
NO VBAT > 4.2V
NO VBAT > 5.5V
YES
YES
CONSTANT VOLTAGE MODE YES
NiMH CHARGER OFF GATEIN = HIGH
NO END OF CHARGE VSENSE < 14mV YES VBAT > 5.5V
NO
YES EOC = HIGH
TERMINATE CHARGE CHGEN = HIGH GATEIN = HIGH
Figure 5. Battery Charger Flow Chart
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REV. 0
ADP3522
Applying an external charger can also turn the handset on. This will turn on all the LDOs, except the SIM LDO, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs.
Deep Discharge Lockout (DDLO) Overtemperature Protection
The DDLO block in the ADP3522 shuts down the handset in the event that the software fails to turn off the phone when the battery voltage drops below 2.9 V to 3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the battery. The DDLO will also shut down the RTC LDO when the main battery is removed. This will prevent reverse current from discharging the backup coin cell.
Undervoltage Lockout (UVLO)
The maximum die temperature for the ADP3522 is 125C. If the die temperature exceeds 160C, the ADP3522 will disable all the LDOs except the RTC LDO. The LDOs will not be re-enabled before the die temperature is below 125C, regardless of the state of PWRONKEY, PWRONIN, and CHRDET. This ensures that the handset will always power off before the ADP3522 exceeds its absolute maximum thermal ratings.
Battery Charging
The ADP3522 battery charger can be used with lithium ion (Li+) and nickel metal hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software. The charger block works in three different modes: 1. Low current (trickle) charging 2. Lithium ion charging 3. Nickel metal hydride charging See Figure 5 for the charger flow chart.
Charge Detection
The UVLO function in the ADP3522 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery is greater than 3.2 V, such as inserting a fresh battery, the UVLO comparator trips, and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below 3.0 V. Once the system is started and the core and memory LDOs are up and running, the UVLO function is entirely disabled. The ADP3522 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor, which usually shuts the phone off at a battery voltage of around 3.0 V. If the handset is off and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3522 into UVLO shutdown mode. In this mode, the ADP3522 draws very low quiescent current, typically 30 A. In DDLO mode, the ADP3522 draws 15 A of quiescent current. NiMH batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 V, which will degrade the batteries' performance. Lithium ion batteries will lose their capacity if overdischarged repeatedly, so minimizing the quiescent currents helps prevent battery damage.
RESET
The ADP3522 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 100 mV, the CHRDET output will go high. If the adapter is then removed and the voltage at the CHRIN pin drops to only 50 mV above the BATSNS pin, CHRDET goes low. The CHRDET signal is not asserted if the battery voltage is below the UVLO threshold.
Trickle Charging
When the battery voltage is below the UVLO threshold, the charge current is set to the low current limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by
ICHR(TRICKLE ) = 20 mV RSENSE
(2)
The ADP3522 contains a reset circuit that is active both at power-up and power-down. The RESET pin is held low at initial power-up. An internal power good signal is generated by the core LDO when its output is up, starting the reset delay timer. The delay is set by an external capacitor on RESCAP: tRESET = 1.2 ms x CRESCAP nF (1)
Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold. Once the UVLO threshold has been exceeded, the charger will switch to the default charge mode, the LDOs will start up, and the baseband processor will start to run. The processor must then poll the battery to determine which chemistry is present and set the charger to the proper mode. Control of the charge mode, Li+ or NiMH, is determined by the CHGEN input.
At power-off, RESET will be kept low to prevent any baseband processor starts.
REV. 0
-15-
ADP3522
4.2V
processor can charge a NiMH battery. Note that when charging NiMH cells, a current limited adapter is required. During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached. Then the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected.
VBAT
3.2V
HIGH CURRENT
Battery Voltage Monitoring
ICHARGE LOW CURRENT 0 EOC CURRENT
The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider can be connected to BATSNS when both the digital and analog baseband sections are powered up. To enable MVBAT, both PWRONIN and TCXOEN must be high. The ratio of the voltage divider is selected so that the 2.4 V maximum input of the AD6521's auxiliary ADC will correspond with the maximum battery voltage of 5.5 V. The divider will be disconnected from the battery when the baseband sections are powered down.
EOC INDICATOR
Figure 6. Lithium Ion Charging Diagram
Lithium Ion Charging
APPLICATION INFORMATION Input Capacitor Selection
For lithium ion charging, the CHGEN input must be low. This allows the ADP3522 to continue charging the battery at the full current. The full charge current can be calculated by using
ICHR( FULL ) = 160 mV RSENSE
(3)
For the input (VBAT, VBAT2, and VRTCIN) of the ADP3522, a local bypass capacitor is recommended; use a 10 F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 F tantalum capacitor with a small (1 F to 2 F) ceramic in parallel. Separate inputs for the SIM LDO and the RTC LDO are supplied for additional bypassing or filtering. The SIM LDO has VBAT2 as its input and the RTC LDO has VRTCIN.
LDO Capacitor Selection
If the voltage at BATSNS is below the charger's output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 14 mV, then an end of charge signal is generated--the EOC output goes high (see Figure 6). The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN pin high and the CHGEN pin high.
NiMH Charging
The performance of any LDO is a function of the output capacitor. The core, memory, SIM, and analog LDOs require a 2.2 F capacitor and the TCXO LDO requires a 0.22 F capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR (anyCAP(R) technology). The ADP3522 is stable with extremely low ESR capacitors (ESR ~ 0) such as multilayer ceramic capacitors (MLCC), but care should be taken in their selection. Note that the capacitance of some capacitor types shows wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, capacitor is recommended. The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 F ceramic capacitor is recommended for stability and best performance.
For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the
-16-
REV. 0
ADP3522
CHARGE CHARACTERISTIC 2.00 1.75 1.8 1.50 1.25
VBAT - V
VBAT - V
CHARGER CHARACTERISTIC 2.0 1.9
1.7 1.6 1.5 1.4 1.3 1.2 1.1
1.00 0.75 0.50 0.25 0 0 20 40 60 TIME - Minutes 80 100 120
1.0 0.9 0 5 10 15 20 25 30 35 40 TIME - Hours
Figure 7. Kanebo PAS621 Charge Characteristic
CHARGER CHARACTERISTIC 2.00 1.75 1.50 1.25
VBAT - V
Figure 10. Seiko TS621 Charge Characteristic
RTC Backup Coin Cell Selection
The choice of the backup cell is based upon size, cost, and capacity. It must be able to support the RTC module's current requirement and voltage range, as well as handle the charge current supplied by the ADP3522 (see TPC 2). Check with the coin cell vendor if the ADP3522's charge current profile is acceptable. Some suitable coin cells are the electric double layer capacitors available from Kanebo (PAS621), Seiko (XC621), or Panasonic (EECEM0E204A). They have a small physical size (6.8 mm diameter) and a nominal capacity of 0.2 F to 0.3 F, giving hours of backup time. Rechargeable lithium coin cells, such as the TC614 from Maxell or the TS621 from Seiko, are also small in size but have higher capacity than the double layer capacitors, resulting in longer backup times. Typical charge curves for each cell type are shown in Figures 7 through 10. Note that the rechargeable lithium type coin cells generally come precharged from the vendor.
RESET Capacitor Selection
1.00 0.75 0.50 0.25 0 0 20 40 60 TIME - Minutes 80 100 120
Figure 8. Panasonic EECEM0E204A Charge Characteristic
CHARGE CHARACTERISTIC 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0 5 10 15 TIME - Hours 20 25 30
RESET is held low at power up. An internal power-good signal starts the reset delay when the core LDO is up. The delay is set by an external capacitor on RESCAP: tRESET = 1.2 ms x CRESCAP nF (4)
A 100 nF capacitor will produce a 120 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VCORE is off to minimize power consumption. When VCORE is on, RESET is capable of driving 500 A.
Setting the Charge Current
VBAT - V
The ADP3522 is capable of charging both lithium ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For lithium ion batteries, the charge
Figure 9. Maxell TC614 Charge Characteristic
REV. 0
-17-
ADP3522
current is programmed by selecting the sense resistor, R1 (see Figure 2). The lithium ion charge current is calculated using The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using:
PDISS = VADAPTER( MAX ) - VDIODE - VSENSE
(5)
ICHR =
VSENSE 160 mV = R1 R1
- UVLO x ICHR
(12)
where VSENSE is the high current limit threshold voltage. Or if the charge current is known, R1 can be found: R1 = VSENSE 160 mV = ICHR ICHR (6)
Similarly the trickle charge current and the end of charge current can be calculated:
ITRICKLE = VSENSE 20 mV = R1 R1
(7) (8)
It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case, the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an overspecified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MIN) = 5.0 V VADAPTER(MAX) = 6.5 V VDIODE = 0.5 V at 800 mA VGATEDR = 0.5 V VSENSE = 160 mV VGS = 5 V - 0.5 V - 0.160 V = 4.3 V. So choose a low threshold voltage FET.
VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT
IEOC =
VSENSE 14 mV = R1 R1
Example: Assume an 800 mA-H capacity lithium ion battery and a 1 C charge rate. R1 = 200 m . Then ITRICKLE = 100 mA and IEOC = 70 mA. Appropriate sense resistors are available from the following vendors: * Vishay Dale * IRC * Panasonic
Charger FET Selection
(13)
VDS = 5 V - 0.5 V - 0.160 V - 4.2 V = 140 mV
The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and charge current. The selected PMOS must satisfy the physical, electrical, and thermal design requirements. To ensure proper operation, the minimum VGS the ADP3522 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following:
VGS = VADAPTER( MIN ) - VGATEDR - VSENSE
RDS ( ON ) =
VDS ICHR( MAX )
=
140 mV = 175 m 800 mA
(14)
PDISS = (VADAPTER( MAX ) - VDIODE - VSENSE - UVLO) x ICHR
(9)
where VADAPTER(MIN) is the minimum adapter voltage. VGATEDR is the gate drive "low" voltage, 0.5 V. VSENSE is the maximum high current limit threshold voltage. The difference between the adapter voltage (VADAPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the on resistance of the FET at maximum charge current.
PDISS = (6.5V - 0.5V - 0.160 V - 3.2V ) x 0.8 A = 2.1W
(15)
Appropriate PMOS FETs are available from the following vendors: * * * Siliconix IR Fairchild
VDS = VADAPTER - VDIODE - VSENSE - VBAT
Then the RDS(ON) of the FET can be calculated:
(10)
Charger Diode Selection
RDS ( ON ) =
VDS ICHR( MAX )
(11)
The diode, D1, shown in Figure 2 is used to prevent the battery from discharging through the PMOS' body diode into the charger's internal bias circuits. A Schottky diode is recommended to minimize the voltage difference from the charger to the battery and the power dissipation. Choose a diode with a current rating high enough to handle the battery charging current and a voltage rating greater than VBAT. The blocking diode is required for both lithium and nickel battery types.
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REV. 0
ADP3522
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT, VBAT2, and VRTCIN pins of the ADP3522. Locate the input capacitor as close to the pins as possible. 2. VAN and VTCXO output capacitors should be returned to AGND. 3. VCORE, VMEM, and VSIM output capacitors should be returned to DGND. 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 6. Kelvin connect the charger's sense resistor by running separate traces to the CHRIN pin and ISENSE pin. Make sure the traces are terminated as close to the resistor's body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3522 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance.
LFCSP Layout Considerations
path to the inner or bottom layers. See Figure 12 for the recommended via pattern. Note that the via diameter is small. This is to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. Note that the thermal pad is attached to the die substrate; the thermal planes that the vias attach the package to must be electrically isolated or connected to VBAT. Do NOT connect the thermal pad to ground. 3. The solder mask opening should be about 120 microns (4.7 mils) larger than the pad size resulting in a minimum 60 microns (2.4 mils) clearance between the pad and the solder mask. 4. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the large size of the thermal pad, eliminating voids may not be possible. Also, if the solder paste coverage is too large, solder joint defects may occur. Therefore, it is recommended to use multiple small openings over a single big opening in designing the paste mask. The recommended paste mask pattern is given in Figure 13. This pattern will result in about 80% coverage, which should not degrade the thermal performance of the package significantly. 5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A "No Clean," Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220C and the time above liquids is less than 75 seconds. The preheat ramp should be 3C/second or lower. The actual temperature profile depends on the board's density and must be determined by the assembly house as to what works best.
The CSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. In order to achieve the optimum performance from the CSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the CSP package: 1. The pad pattern is given in Figure 11. The pad dimension should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging. 2. The thermal pad of the CSP package provides a low thermal impedance path (approximately 15C/W) to the PCB. Therefore, the PCB must be properly designed to effectively conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal
REV. 0
-19-
ADP3522
0.08 3.80 5.36 3.96 3.56 0.70 0.30 0.50
CREATE SOLDER PASTE WEB FOR APPROX 80% COVERAGE 125 MICRONS WIDE TO SEPARATE SOLDER PASTE AREA THERMAL PAD AREA
Dimensions shown in millimeters
Figure 11. 5 mm
5 mm LFCSP Pad Pattern
ARRAY OF 9 VIAS 0.25mm DIAMETER 0.35 m PLATING
Figure 13. 5 mm
5 mm LFSCP Solder Paste Mask Pattern
0.60 1.18 1.18 0.60
THERMAL PAD AREA
Dimensions shown in millimeters
Figure 12. 5 mm
5 mm LFSCP Via Pattern
OUTLINE DIMENSIONS 32-Lead Frame Chip Scale Package [LFCSP] 5 mm 5 mm Body
Dimensions shown in millimeters
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 12 MAX 1.00 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
17 16
9
3.50 REF
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
-20-
REV. 0
PRINTED IN U.S.A.
1.00 0.90 0.80
0.30 0.23 0.18
C03535-0-2/03(0)
0.20

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